Analogue AI Chips: How In-Memory Computing Reduces Neural Network Energy Consumption

Artificial intelligence is becoming more demanding, and the electricity required to run neural networks is an increasingly important concern. Conventional processors spend considerable energy transferring information between memory and computing units, particularly when handling models containing millions or billions of parameters. Analogue AI chips offer a different approach: they perform calculations directly within memory circuits, reducing unnecessary data transfers. This technique, known as analogue in-memory computing, could make AI systems faster and more energy-efficient. Research published between 2023 and 2026 has demonstrated its potential in speech recognition, language processing and other neural network applications. However, converting promising laboratory results into reliable, widely available hardware remains a significant engineering challenge.

How Analogue AI Chips Change the Way Neural Networks Work

Most modern AI systems rely on digital processors, including graphics processing units (GPUs), to perform enormous numbers of mathematical operations. These processors are particularly effective at handling complex calculations simultaneously, but they still need access to the information stored in memory. Each time a neural network processes an image, recognises speech or generates text, the processor repeatedly retrieves model parameters and processes incoming data. Moving that information consumes electricity and takes time. As neural networks become larger, the cost of transferring data can become a substantial part of their overall energy requirements, even when the calculations themselves are highly efficient.

Analogue AI chips address this problem by bringing computation and storage into the same physical location. Instead of continuously transferring numerical values to a separate processing unit, specialised memory circuits participate directly in calculations. Electrical properties such as voltage, current and conductance represent information and help perform mathematical operations. This does not mean abandoning digital computing completely. Most practical designs combine analogue memory arrays with digital circuits responsible for controlling operations, processing results and communicating with other components. The main objective is to reduce the energy spent moving data while preserving the accuracy required for useful AI applications.

This approach is particularly well suited to neural networks because many of their operations involve multiplying numbers and adding the results together. These calculations determine how strongly different pieces of information influence the output of a model. Conventional hardware performs them through sequences of digital instructions, whereas an analogue memory array can carry out many related operations simultaneously through the behaviour of its electrical circuits. Consequently, the chip can process certain AI workloads with fewer conventional computing steps. The improvement depends on the type of neural network, the memory technology and the supporting circuitry, so analogue processing should be considered a specialised method rather than a universal replacement for existing processors.

Why Computing Inside Memory Can Save Electricity

To understand the energy savings, consider a neural network recognising a spoken command. Its internal connections contain numerical values known as weights, which determine how the network responds to different sound patterns. A conventional processor must access these values repeatedly while analysing the incoming audio. An analogue in-memory chip stores the weights inside circuits that also perform the necessary calculations. Incoming signals interact with these stored values, producing electrical outputs that represent the results. Because the weights do not have to travel back and forth between separate memory and computing units for every operation, the system can reduce both data movement and the associated energy consumption.

One widely studied design uses a crossbar array, a network of intersecting electrical connections containing memory devices. Each device can represent a neural network weight through its electrical conductance, which describes how readily current passes through it. When input voltages are applied, currents flowing through the array correspond to mathematical products, while the combined currents naturally represent their sums. This behaviour allows the hardware to perform matrix–vector multiplication, a fundamental operation in neural networks. Although the underlying physics involves electrical resistance and current, the principle is straightforward: the physical behaviour of the memory circuit performs part of the mathematics that digital processors would otherwise calculate separately.

Energy savings are not automatic, however. Analogue chips still require circuits that prepare input signals, convert electrical outputs into digital values and coordinate information between different memory arrays. These supporting components consume electricity, and their contribution can become significant when a model requires frequent conversions or additional processing. Engineers therefore assess the complete chip rather than the memory array alone. A useful comparison must also consider accuracy, processing speed and the amount of work completed. An analogue circuit that performs individual operations efficiently may provide a smaller advantage when its supporting electronics and communication requirements are included in the overall measurement.

Memory Technologies and Research Achievements Behind Analogue AI

Several memory technologies are being investigated for analogue AI computing, each offering a different balance of efficiency, accuracy and manufacturing complexity. Phase-change memory is among the most extensively demonstrated approaches. It uses materials whose electrical resistance changes when their internal structure is altered by carefully controlled electrical pulses. These changes allow individual memory devices to represent numerical weights used by neural networks. The stored values can remain available without a continuous power supply, making phase-change memory attractive for certain energy-conscious designs. However, programming these values accurately and maintaining their stability over time require careful engineering.

Resistive memory, often associated with memristors, provides another possibility. These devices can change their resistance according to previously applied electrical signals, allowing them to store information and participate in calculations. Researchers are also investigating circuits based on static random-access memory (SRAM), charge storage and combinations of different memory types. SRAM is already widely used in conventional processors, but analogue operations inside SRAM-based circuits introduce different design compromises. Some emerging non-volatile memories offer compact storage, while SRAM can provide predictable digital behaviour. Selecting the right technology depends on the required precision, available manufacturing processes, operating conditions and the neural network being accelerated.

Importantly, analogue memory is not restricted to storing one continuously adjustable value in every device. Some designs combine several devices or use multiple electrical measurements to represent a numerical weight more accurately. Others divide calculations between analogue and digital circuits, allowing each technology to handle the operations it performs most effectively. This flexibility has encouraged the development of mixed-signal AI processors, which combine both types of circuitry. Rather than treating analogue and digital computing as competing solutions, researchers increasingly examine how they can cooperate. Such arrangements can preserve the energy advantages of computing inside memory without requiring every stage of a neural network to operate through analogue signals.

What IBM and Recent Scientific Studies Have Demonstrated

One important demonstration came from IBM Research in 2023. In a study published in Nature, researchers described a 14-nanometre analogue AI chip containing approximately 35 million phase-change memory devices arranged across 34 computing tiles. The chip achieved a reported sustained performance of up to 12.4 trillion operations per second per watt. Researchers demonstrated accurate keyword recognition and used five interconnected chips to process a considerably larger speech transcription network involving more than 45 million weights. These results showed that analogue in-memory computing could support meaningful neural network workloads, rather than simply performing isolated mathematical demonstrations. The reported efficiency figure describes the experimental hardware under specific conditions, not a guaranteed improvement over every commercial GPU.

Progress continued in 2025. Research published in Nature described a mixed-precision AI processor combining memristor computing with SRAM-based computing, addressing the difficulty of maintaining accuracy while benefiting from compact, energy-efficient memory. In September 2025, IBM researchers also reported running an ALBERT language model on an analogue inference chip, with 7.1 million unique weights represented using approximately 28.3 million devices. Across the reported language-understanding tests, the average hardware accuracy was 1.8 percentage points below the floating-point reference. The study demonstrated that careful adjustment of a model and compensation for hardware imperfections could make analogue execution practical for more sophisticated language-processing tasks.

By 2026, scientific attention had increasingly turned towards overcoming the remaining obstacles to reliable operation. A review published in Nature Materials in May 2026 examined how noise, device variability and circuit imperfections affect memristor-based analogue computing. It also considered ways to improve accuracy without sacrificing too much of the original energy advantage. Another notable 2025 study in Nature Computational Science investigated analogue in-memory calculations for the attention mechanism used in language models. Its specialised architecture reported very large reductions in attention-related energy consumption compared with the GPU implementations examined. Such results demonstrate considerable potential, but they apply to particular operations and experimental designs, not necessarily the total electricity consumed by a complete language model.

Practical Applications, Limitations and the Future of Analogue AI Chips

Smaller, energy-efficient AI systems are among the most promising applications for analogue in-memory computing. Smartphones, wearable devices, security cameras and industrial sensors often need to analyse information without relying continuously on remote servers. A device that can recognise a voice command, detect an unusual sound or identify an object locally may respond faster and transmit less information over a network. Lower energy requirements could also help battery-powered devices operate for longer between charges. However, the benefit depends on whether the neural network fits the available memory, how often it runs and whether the surrounding electronics consume more energy than the specialised calculations save.

Healthcare equipment and industrial monitoring systems present additional possibilities. A compact AI chip could help analyse signals from medical sensors, identify unusual machine vibrations or process information from environmental monitoring equipment. In these applications, low power consumption can be valuable because devices may need to operate continuously or in locations where replacing batteries is inconvenient. Local processing can also reduce the need to send sensitive or time-critical information elsewhere. Nevertheless, hardware efficiency does not establish medical reliability or industrial safety. Systems used in critical environments require rigorous testing, appropriate safeguards and validation under realistic operating conditions before they can be trusted for important decisions.

Large computing facilities could eventually benefit from analogue accelerators, especially when processing tasks involve repeatedly applying established neural network weights. This activity, called inference, occurs whenever a trained model generates predictions or responses. Inference is particularly attractive because the weights may remain unchanged for many calculations. Training a model is more complicated: its weights must be updated repeatedly as the system learns, potentially increasing the energy and time required to programme analogue memory devices. Consequently, analogue accelerators are currently more mature for selected inference workloads than for general-purpose large-scale training. Future computing systems may use conventional processors alongside specialised analogue chips, assigning different tasks to whichever hardware performs them most efficiently.

Challenges That Must Be Solved Before Widespread Adoption

The largest technical difficulty is maintaining reliable numerical accuracy. Digital processors represent information using precisely defined states, while analogue circuits operate with physical quantities that are affected by electrical noise, temperature, manufacturing differences and gradual changes in materials. Two memory devices programmed to represent the same value may behave slightly differently. Some technologies also experience conductance drift, meaning stored electrical characteristics change over time. These imperfections can introduce errors into neural network calculations, particularly when many operations are connected together. Engineers address the problem through calibration, improved circuit design, carefully selected numerical precision and training techniques that account for the behaviour of real hardware.

Manufacturing and software compatibility create further challenges. Conventional AI software has been developed around CPUs, GPUs and established digital accelerators, making it relatively straightforward to run supported models across widely available hardware. Analogue chips require additional tools to translate neural networks into suitable memory configurations and manage the relationship between physical signals and digital calculations. Developers must also consider the lifespan of memory devices, the number of times weights can be rewritten, production costs and integration with existing semiconductor manufacturing processes. Even a highly efficient experimental design may struggle commercially if manufacturing yields are low, programming is slow or its advantages disappear when connected to a complete computing system.

As of October 2026, analogue in-memory computing remains an active research and development field rather than a general replacement for conventional AI processors. Its strongest advantage is a clear physical principle: performing calculations where neural network weights are stored can eliminate substantial amounts of unnecessary data movement. Published demonstrations have already shown useful results in speech processing, language understanding and specialised neural network operations. The next stage depends on translating those achievements into chips that are accurate, affordable, reliable and easy to integrate into real products. If engineers can balance these requirements, analogue AI hardware could become an important part of more energy-efficient computing, particularly where electricity consumption, heat and battery life place practical limits on AI applications.